Nov-14: A number of notes about the final project:
The RAM and EEPROM devices of our circuit simulator allows you to choose the bit width of the addresses it
accepts, and then creates a capacity to match 2width bytes of addressable memory. This bit width is
limited to 20 bits for the RAM devices, and 10 bits for the EEPROM devices, meaning they can contain at most 1 MB and 1
KB, respectively. These addresses are not as wide as our 32-bit addresses native to RISC-V. Since we are already
implementing a limited subset of RISC-V, this is another place in which we can limit what our simulated processors can
do. Specifically, the addresses specified in our programs will remain 32 bits, but only the the lowest bits (matching
the device) should actually be used. This is sufficient for our testing purposes.
Similarly, if you've only implemented (say) 8 registers in your register file so far, you can actually build around this
structure with the temporary limitation that only the first 8 registers are actually usable. This is a good shortcut
for debugging the rest of the design, allowing you to fill out the register file later with all 32 registers.
Some of the opcodes that I listed are pseudo-instructions, which are instruction formats that can be expressed in
assembly code, but are then translated by the assembler into instructions using a different (and real) opcode that the
processor will execute. Which pseudo-instructions are available depends on the assembler. Specifically, here are ones
you may have seen of which you should be aware:
not t0, t1 is translated into xor t0, t1, -1. That is, there's no need for a not opcode,
since performing a bitwise xor with a constant of all 1's (which is -1 in two's complement) is
subi t0, t1, 15 is translated into addi t0, t1, -15. Obvious.
ble t0, t1, Label is translated into bge t1, t0, Label. That is, inequality in one direction is
the same as inequality in the other direction with the operands reversed. For RISC-V, only bge is real.
bgt t0, t1, Label is translated into blt t1, t0, Label. Same as above, but for strict
inequalities, where only blt is real.
move t0, t1 is translated into add t0, t1, zero. Obvious.